Nitride-based semiconductor module and method for manufacturing the same

ABSTRACT

The present disclosure provides a semiconductor module comprising a semiconductor device removably pressed-fit in a cavity formed in a printed circuit board and methods for manufacturing the same. The semiconductor device and the cavity of the printed circuit board can cooperate with each other and act as an electrical plug and an electrical socket respectively. Soldering the semiconductor device on the printed circuit board can be avoided. Therefore, the packaging process can be more flexible and reliability issues with solder joints can be eliminated. Moreover, heatsink can be mounted on top and/or bottom of the semiconductor device after being received in the cavity of the printed circuit board. Thermal dissipation efficiency can be greatly enhanced.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application of U.S.Non-Provisional patent application Ser. No. 17/624,355 filed Jan. 3,2022, and the disclosure of which is incorporated herein by reference inits entirety.

FIELD OF THE INVENTION

The present invention generally relates to an electronic devicepackaging. More specifically, the present invention relates to anitride-based semiconductor module including a nitride semiconductordevice fitted in a printed circuit board (PCB) and to methods formanufacturing the PCB and the semiconductor device.

BACKGROUND OF THE INVENTION

Nitride semiconductor device such as gallium nitride (GaN) devices areprevalent in developments in semiconductor technologies and devices suchas high power switching and high frequency applications. Conventionally,a nitride semiconductor device is packaged in a leaded or leadlesspackage and assembled in a printed circuit board (PCB) by means ofthrough-hole mounting or surface-mount mounting. Both types of processesrequire use of solder to provide electrical connection between thecomponents and the PCB. Due to the mismatch between coefficients ofthermal expansion of the soldering joint and the PCB, the solderingjoint may be degraded and have reliability problems in power cycling.The thermal dissipation paths through the PCB are not sufficient todissipate heat generated by the devices for high power switching andhigh frequency applications. Furthermore, the lead of leaded packagehave parasitic impedance and reactance that limit the high frequencyperformance. Therefore, there is a need to improve package designs fornitride semiconductor devices, thereby making them more flexible formass production and more reliable.

SUMMARY OF THE INVENTION

An object of the present disclosure is to provide an electronic packageand a method for manufacturing the same, which can address the abovesaid reliability and parasitic impedance and reactance issues.

In accordance with one aspect of the subject application, anitride-based semiconductor module comprising a nitride-based deviceremovably pressed-fit in a cavity formed in a printed circuit board andmethods for manufacturing the same are provided. The nitride-basedsemiconductor device and the cavity of the printed circuit board cancooperate with each other and act as an electrical plug and anelectrical socket respectively. Soldering the nitride-based device onthe printed circuit board can be avoided. Therefore, the packagingprocess can be more flexible and reliability issues with solder jointscan be eliminated. Moreover, heatsink can be mounted on top and/orbottom of the semiconductor device after being received in cavity of theprinted circuit board. Thermal dissipation efficiency can be greatlyenhanced.

In accordance with another aspect of the subject application, thesemiconductor device comprises: a nitride-based chip having an activesurface formed with a plurality of conductive pads and a passive surfaceopposite to the active surface; an enclosure enclosing the nitride-basedchip and having a top surface, a bottom surface and a plurality of sidesurfaces; and a plurality of conductive paths configured forelectrically connecting the nitride-based chip to an external system,respectively having a plurality of exterior conductive contacts exposedon the plurality of side surfaces and extending over and along theplurality of side surfaces from the top surface to the bottom surface ofthe enclosure. The enclosure has a shape conformal to a shapesubstantially conformal to a shape of the nitride-based chip to achievea chip-scale package. The plurality of exterior conductive contacts areelectrically couplable with a plurality of interior conductive leads ina cavity of a printed circuit board such that the nitride-basedsemiconductor device can act as an electrical plug cooperating anelectrical socket acted by the cavity of the printed circuit board.

In accordance with yet another aspect of the subject application, theprinted circuit board comprises: an upper surface; a lower surfaceopposite to the upper surface; one or more substrate layers arrangedbetween the upper surface and the lower surface; a cavity having one ormore interior sidewalls being substantially perpendicular to the upperand lower surfaces; and a plurality of interior conductive leads fixedon and extending from the upper surface of the printed circuit board andbending into the cavity. The cavity of the printed circuit board has ashape conformal to a shape of an enclosure of the nitride-basedsemiconductor device such that the nitride-based semiconductor devicecan be removably press-fitted into the cavity of the printed circuitboard. The plurality of interior conductive leads in the cavity of theprinted circuit board are configured to be resiliently contactable toand electrically couplable with a plurality of exterior conductivecontacts of the nitride-based semiconductor device such that the cavitycan act as an electrical socket cooperating with an electrical plugacted by the nitride-based semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present disclosure are described in moredetail hereinafter with reference to the drawings, in which:

FIG. 1A is a simplified top view of a semiconductor module according toan embodiment of the present disclosure, and FIG. 1B is across-sectional view of the semiconductor module taken along the cuttingline A-A′ in FIG. 1A;

FIG. 2 is a cross-sectional view of an electronic assembly mounted withheatsinks according to an embodiment of the subject application;

FIG. 3A is a simplified top view of semiconductor module according toanother embodiment of the present invention and FIG. 3B is a crosssectional view taken along the cutting line A-A′ in the FIG. 3A;

FIG. 4 is a cross-sectional view of an electronic assembly mounted withheatsink according to another embodiment of the subject application;

FIG. 5A shows more details of the top view the semiconductor device inFIG. 1A, and FIG. 5B shows more details of the cross-sectional view ofthe semiconductor device in FIG. 1B;

FIG. 6A is a top view of a semiconductor device according to anotherembodiment of the present invention and FIG. 6B is a cross sectionalview taken along the cutting line A-A′ in the FIG. 6A;

FIG. 7A, FIG. 7B, FIG. 7C, FIG. 7D, FIG. 7E, FIG. 7F, FIG. 7G, and FIG.7H depict steps of a method for manufacturing a plurality ofsemiconductor devices according to the embodiment of FIG. 5A and FIG.5B;

FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, FIG. 8E, FIG. 8F, FIG. 8G, and FIG.8H depict steps of a method for manufacturing a plurality ofsemiconductor devices according to the embodiment of FIG. 6A and FIG.6B;

FIG. 9A shows more details of the top view of the printed circuit boardof FIG. 1A and FIG. 9B shows more details of the cross-sectional view ofthe printed circuit board of FIG. 1B;

FIG. 10A and FIG. 10B illustrate how a semiconductor device is fittedinto the printed circuit board of FIG. 9A and FIG. 9B;

FIG. 11A, FIG. 11B and FIG. 11C depict steps of a method formanufacturing a printed circuit board according to the embodiment ofFIG. 9A and FIG. 9B;

FIG. 12A shows more details of the top view of the printed circuit boardof FIG. 2A and FIG. 12B shows more details of the cross-sectional viewof the printed circuit board of FIG. 2B;

FIG. 13A and FIG. 13B illustrate how a semiconductor device is fittedinto the printed circuit board of FIGS. 12A and 12B;

FIG. 14A, FIG. 14B and FIG. 14C depict steps of a method formanufacturing a printed circuit board according to the embodiment ofFIG. 12A and FIG. 12B.

It should be noted that various features may not be drawn to scale. Infact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

DETAILED DESCRIPTION

Preferred embodiments of the present disclosure will be readilyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings. Common reference numerals are usedthroughout the drawings and the detailed description to indicate thesame or similar components.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,”“down,” “first,” “second,” “vertical,” “horizontal,” “side,” “higher,”“lower,” “upper,” “over,” “under,” and so forth, are specified withrespect to a certain component or group of components, or a certainplane of a component or group of components, for the orientation of thecomponent(s) as shown in the associated figure. It should be understoodthat the spatial descriptions used herein are for purposes ofillustration only, and that practical implementations of the structuresdescribed herein can be spatially arranged in any orientation or manner,provided that the merits of embodiments of this disclosure are notdeviated from by such arrangement.

Further, it is noted that the actual shapes of the various structuresdepicted as approximately rectangular may, in actual device, be curved,have rounded edges, have somewhat uneven thicknesses, etc. due to devicefabrication conditions. The straight lines and right angles are usedsolely for convenience of representation of layers and features.

In the following description, a semiconductor module comprising asemiconductor device removably pressed-fit in a printed circuit boardand methods for manufacturing the same, and the likes are set forth aspreferred examples. It will be apparent to those skilled in the art thatmodifications, including additions and/or substitutions may be madewithout departing from the scope and spirit of the present disclosure.Specific details may be omitted so as not to obscure the presentdisclosure; however, the disclosure is written to enable one skilled inthe art to practice the teachings herein without undue experimentation.

FIG. 1A is a simplified top view of a semiconductor module 10A accordingto an embodiment of the present disclosure, and FIG. 1B is across-sectional view of the semiconductor module 10A taken along thecutting line A-A′ in FIG. 1A.

The semiconductor module 10A may comprise a printed circuit board 50A.The printed circuit board 50A may be a multi-layer board with conductivelayers that are patterned and formed between substrate layers that canbe fiberglass or other insulating substrate layers. The printed circuitboard 50A may have a cavity 510A and a plurality of interior conductiveleads 520 extending from a surface 501 of the printed circuit board 50Aand bending into the cavity 510A.

The semiconductor device 30A may have an enclosure 31A and a pluralityof exterior conductive contacts 341 exposed on a plurality of sidesurfaces 303 of the enclosure 31A.

The cavity 510A of the printed circuit board 50A and the enclosure 31Aof semiconductor device 30A may have their shapes conformal to eachother such that the semiconductor device 30A may be removablypress-fitted into the cavity 510A of the printed circuit board 50A.

The plurality of exterior conductive contacts 341 of the semiconductormay be configured to be resiliently contactable to and electricallycouplable with the plurality of interior conductive leads 520 in thecavity 510A of the printed circuit board 50A such that the semiconductordevice 30A may act as an electrical plug cooperating with the cavity510A which act as an electrical socket.

Referring to FIG. 2. In some embodiments, after the semiconductor device30A being fitted into the cavity 510A of the printed circuit board 50A,a first heatsink 910A may be mounted on a top surface of thesemiconductor device 30A and a second heatsink 920A on a bottom surfaceof the semiconductor device 30A.

FIG. 3A is a simplified top view of semiconductor module 10B accordingto another embodiment of the present invention and FIG. 3B is a crosssectional view taken along the cutting line A-A′ in the FIG. 3A. Thesemiconductor module 10B of FIGS. 3A-3B is similar to the semiconductormodule 10A of FIGS. 1A-1B except for that the semiconductor module 10Bcomprises a printed circuit board 50B having a cavity 510B that has ablind-hole structure. For simplicity, identical elements in FIGS. 3A-3Band FIGS. 1A-1B are given the same reference numerals and will not befurther described in details.

Referring to FIG. 4. In some embodiments, after the semiconductor device30A being fitted into the cavity 510B of the printed circuit board 50B,a heatsink 910B may be mounted on a top surface of the semiconductordevice.

It should be understood that the semiconductor module may furthercomprise other electronic components mounted to the printed circuitboard. The other electronic components may include semiconductor or ICdevices of various kinds, transistors, diodes, passive electroniccomponents such as resistors, capacitors, resistor packs, inductors,transformers, and other components such as connectors, jumper wires,posts, handles, guides, mechanical supports, and mechanical devices.

FIG. 5A shows more details of the top view the semiconductor device 30Aof FIG. 1A, and FIG. 5B shows more details of the cross-sectional viewof the semiconductor device 30A.

The semiconductor device 30A may comprise a semiconductor chip 310, anenclosure 31A enclosing the semiconductor chip 310 and configured forprotecting the semiconductor chip; and a plurality of conductive paths32A configured for electrically connecting the semiconductor chip 310 toan external system (not shown).

The semiconductor chip may have an active surface 311 formed with aplurality of conductive pads 313; and a passive surface 312 opposite tothe active surface.

In various embodiments, the semiconductor chip 310 may be, for examplebut not limited to, a nitride-based chip including a plurality ofsemiconductor layers, and the semiconductor layers may include materialssuch as gallium nitride (GaN), aluminum gallium nitride (AlGaN),silicon, or fluorine ions.

The enclosure 31A may having a top surface 301, a bottom surface 302 anda plurality of side surfaces 303. The enclosure 31A may comprise aninsulating layer 320 positioned below the semiconductor chip 310, and anencapsulation layer 330 surrounding the semiconductor chip 310. Theenclosure 31A may be generally formed in a shape substantially conformalto a shape of the semiconductor chip 310 to achieve a chip-scalepackage.

The insulating layer 320 may have a first surface 321 facing thesemiconductor chip 310 and a second surface 322 opposite to the firstsurface 321. The first surface 321 of the insulating layer 320 may be incontact with the active surface 311 of the semiconductor chip 310.

The encapsulation layer 330 may have a first surface 331 adjacent to thepassive surface 312 of the semiconductor chip 310 and a second surface332 opposite to the first surface 331 and adjacent to the second surface322 of the insulating layer 320.

The first surface 331 of the encapsulation layer 330 may besubstantially coplanar with the passive surface 312 of the semiconductorchip 310. As such, the first surface 331 of the encapsulation layer 330and the passive surface 312 of the semiconductor chip 310 form a topsurface of the semiconductor device 30A.

The second surface 332 of the encapsulation layer 330 may besubstantially coplanar with the second surface 322 of the insulatinglayer 320. As such, the second surface 332 of the encapsulation layer330 and the second surface 322 of the insulating layer 320 form a bottomsurface of the semiconductor device 30A.

In some embodiments, the plurality of side surfaces 303 may besubstantially perpendicular to the active surface 311 of thesemiconductor chip 310. That is, the side surfaces 303 may besubstantially forming an angle of 90° with the active surface 311 of thesemiconductor chip 310. In some embodiments, the side surfaces 303 maybe slanted and forming an angle α with the active surface 311 of thesemiconductor chip 310. The angle α may range from approximately 90° toapproximately 135°.

The plurality of conductive paths 32A may comprise a plurality ofexterior conductive contacts 341 exposed on and extending along the sidesurfaces 303 of the enclosure 31A for providing electrical connection toan external circuit (not shown). In some embodiments, the plurality ofexterior conductive contacts 341 may be extending along the entireheight of the side surfaces 303 from the bottom surface 302 to the topsurface 301 of the enclosure 31A.

In some embodiments, the semiconductor device 310 may comprise one ormore seed layers (not shown) respectively disposed under the one or morethe exterior conductive contacts 341 for enhancing adhesion between theexterior conductive contacts 341 and the encapsulation layer.

The plurality of conductive paths 32A may further comprise a pluralityof conductive vias 351 electrically coupled with the conductive pads 313of the semiconductor chip 310 and extending substantially longitudinallyfrom the active surface 311 of the semiconductor chip 310 to the bottomsurface 302 of the enclosure 31A. The plurality of conductive vias maybe formed through the insulating layer from the first surface 321 to thesecond surface 322 of the insulating layer 320.

The plurality of conductive paths 32A may further comprise a pluralityof conductive traces 352 respectively extending from the conductive vias351 and substantially laterally over the bottom surface 302 to the sidesurfaces 303 of the enclosure 31A to electrically couple with exteriorconductive contacts 341. The conductive traces 352 may be formed on thesecond surface 322 of insulating layer 320 and the second surface 332 ofthe encapsulation layer 330.

The conductive traces 352 and the exterior conductive contacts 341 forma cup to receive the semiconductor chip. The cup formed by theconductive traces 352 and the exterior conductive contacts 341 maysurround/enclose the semiconductor chip. The cup formed by theconductive traces 352 and the exterior conductive contacts 341 maysurround/enclose the insulating layer 320. The cup formed by theconductive traces 352 and the exterior conductive contacts 341 maysurround/enclose the encapsulation layer 330.

FIG. 6A is a top view of a semiconductor device 30B according to anotherembodiment of the present invention and FIG. 6B is a cross sectionalview taken along the cutting line A-A′ in the FIG. 6A. The semiconductordevice 30B of FIGS. 6A-6B is similar to the semiconductor device 30A ofFIGS. 5A-5B except for that its encapsulation layer 430 is configured tocompletely encapsulate the semiconductor chip 310. For simplicity,identical elements in FIGS. 6A-6B and FIGS. 5A-5B are given the samereference numerals and will not be further described in details.

As shown in FIGS. 6A and 6B, the encapsulation layer 430 may have afirst surface 431 above the passive surface 312 of the semiconductorchip and a second surface 432 opposite to the first surface 431 andadjacent to the second surface 322 of the insulating layer 320. As such,the first surface 431 of the encapsulation layer form a top surface ofthe semiconductor device 30B (or enclosure).

FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 7G, and 7H depict steps of a method formanufacturing a plurality of semiconductor devices according to theembodiment of FIGS. 5A-5B. For simplicity, only two semiconductordevices are shown in this embodiment. It should be understood that themethod may be used for manufacturing a batch of any number ofsemiconductor devices.

In the step illustrated in FIG. 7A, a baseplate is provided and appliedwith a plurality of insulating adhesives. The baseplate may comprise,but not limited to, a silicon (Si) or silicon carbide (SiC) substrate.The insulating adhesives may be in a form of paste applied on thebaseplate by dispensing or printing processes. Alternatively, theinsulating adhesives may be in a form of films applied on the baseplateby pick-and-place process.

In the step illustrated in FIG. 7B, a plurality of semiconductor chipsare flip-chip boned on the insulating adhesives respectively with theirconductive pads facing the insulating adhesives. The insulatingadhesives may then be cured to secure the semiconductor chips on thebaseplate and form a plurality of insulating layers under thesemiconductor chips respectively.

In the step illustrated in FIG. 7C, encapsulant may be applied to formencapsulation layer to surround the plurality of semiconductor chips andover the insulating layer. The encapsulation layer may have a firstsurface adjacent to and substantially coplanar to the passive surfacesof the semiconductor chips; and a second surface adjacent to andsubstantially coplanar with the second surface of the insulating layer.The encapsulation layer may be applied to surround semiconductor chipswithout covering the passive surfaces of the semiconductor chips.Alternatively, the encapsulation layer may be applied to completelycover the semiconductor chips and then a top portion of theencapsulation layer is removed to expose the passive surfaces of thesemiconductor chips.

In the step illustrated in FIG. 7D, the baseplate is removed, leavingthe second surface of the insulating layers exposed such that the secondsurface of the insulating layers and the second surface of theencapsulation layer together form bottom surfaces of the semiconductordevices.

In the step illustrated in FIG. 7E, one or more conductive vias areformed through the insulating later such that the conductive viassubstantially longitudinally extend from the first surface to the secondsurface of the insulating layer and electrically connected to the one ormore conductive pads of the semiconductor chips respectively.

The formation of conductive vias may comprise: forming through holes inthe insulating layer by a lithographic process and etching process;forming an oxide liner on the sidewalls of the through holes; fillingthe through holes with conductive material such as metal, and thenpolishing to remove excess metal outside the through holes.

In the step illustrated in FIG. 7F, one or more conductive traces areformed on the second surface of the insulating layer and the secondsurface of the encapsulation layer such that the one or more conductivetraces are electrically connected to the conductive vias respectively,and substantially laterally extend over the bottom surface of thesemiconductor devices.

The conductive traces may be formed by deposition of a metallicmaterials using a chemical vapor deposition (CVD) process, an atomiclayer deposition (ALD) process, a physical vapor deposition (PVD),another applicable process, or a combination thereof.

In the step illustrated in FIG. 7G, one or more conductive vias areformed in the encapsulation layer such that the one or more conductivevias are electrically connected to the one or more conductive traces,respectively, and substantially longitudinally extend though theencapsulation layer from the first surface to the second surface of theencapsulation layer.

The formation of conductive vias may comprise: forming through holes inthe encapsulation layer by a lithographic process and etching process;forming an oxide liner on the sidewalls of the through holes; fillingthe through holes with conductive material such as metal, and thenpolishing to remove excess metal outside the through holes.

In the step illustrated in FIG. 7H, the semiconductor devices areseparated from one another by dicing such that the one or moreconductive vias are exposed on and extending substantiallylongitudinally along side surfaces of the semiconductor device to formone or more exterior conductive contacts 341.

FIGS. 8A, 8B, 8C, 8D, 8E, 8F, 8G, and 8H depict steps of a method formanufacturing a plurality of semiconductor devices according to theembodiment of FIGS. 6A-6B. The method as shown in FIGS. 8A, 8B, 8C, 8D,8E, 8F, 8G, and 8H is similar to the method as shown in FIGS. 7A, 7B,7C, 7D, 7E, 7F, 7G, and 7H, except for that in the step of FIG. 8C, theencapsulant may be applied to form encapsulation layer to completelycover the plurality of semiconductor chips and over the insulating layersuch that the encapsulation layer may have a top surface above thepassive surfaces of the semiconductor chips.

FIG. 9A shows more details of the top view of the printed circuit board50A and FIG. 9B is a cross sectional view taken along the cutting lineA-A′ in the FIG. 9A.

The printed circuit board 50A may comprise an upper surface 501 and alower surface 502 opposite to the upper surface. Each of the uppersurface 501 and lower surface 502 may be deposited with a conductivemetal layer patterned with pads 503 and traces 504.

In various embodiments, the printed circuit board may further compriseone or more substrate layers (not shown) arranged between the upper andlower surfaces, each having a conductive metal layer patterned withtraces and pads on both sides and one or more vias for interconnectingthe conductive traces and pads.

The cavity 510A may have a through-hole structure having a top openingat the upper surface of the printed circuit board 50A and a bottomopening at the lower surface of the printed circuit board 50A.

The plurality of interior conductive leads 520 of the printed circuitboard 50A may be a plurality of conductive leads 520 electricallyconnected to the plurality of conductive pads 503 near the cavity 510Aand on the upper surface 501 of the printed circuit board 50A. Each ofthe conductive leads 520 may have a first lead portion 521 fixed on aconductive pad 503 and extending from the conductive pad 503 to an edge511 of the cavity 510A. Each of the conductive leads 520 may furtherhave a second lead portion 522 bending from the first lead portion 521and extending substantially longitudinally downward along an interiorsidewall 503 into the cavity 510A. In some embodiments, each of theconductive leads may further have a third lead portion bending from thesecond lead portion and extending substantially laterally towards acentral region of the cavity.

Referring to FIGS. 10A-10B. When a semiconductor device 30A is insertedinto the cavity 510A of the printed circuit board 50A, the plurality ofinterior conductive leads 520 may be configured to make contact with aplurality of exterior conductive contacts 341 of the semiconductordevice 30A. The plurality of interior conductive leads may be at a firststate where they are not making contact with the exterior conductivecontacts 341 of the semiconductor device 30A; and reversibly change to asecond state where they are making contact with the exterior conductivecontacts 341 of the semiconductor device 30A.

More specifically, the second lead portion 522 is elastically deformableto have a resilient contact with the exterior conductive contacts 341 ofthe semiconductor device when the semiconductor device 30A is insertedinto the cavity. For example, the second lead portion 522 has a curvedsurface at the first state. When the semiconductor device 30A isinserted into the cavity 510A, the second lead portion 522 is pushed bythe semiconductor device 30A and having a movable end 523 flushingagainst the interior sidewall 503 in the cavity 510A such that thesecond lead portion 522 is deformed to have a substantially flat surfacecoupling with the exterior conductive contacts 341 of the semiconductordevice 30A.

Moreover, the conductive leads 520 may have their second lead portions522 being bent at a first bending angle β1 from their first leadportions 521 at the first state; and their second lead portions 522being bent at a second bending angle β2 smaller than the first bendingangle β1 from their first lead portions 521 at the second state.

FIGS. 11A, 11B and 11C depict steps of a method for manufacturing aprinted circuit board according to the embodiment of FIGS. 9A-9B.

In a step illustrated in FIG. 11A, a printed circuit board is providedwith and patterned with conductive traces and pads on an upper surfaceand a bottom surface. The conductive traces and pads may be formed bycopper plating and then do surface finish plating using gold, silver,tin, nickel, or various alloys.

In a step illustrated in FIG. 11B, a through-hole cavity is formed inthe printed circuit board by machine cutting or laser drilling. That is,the cavity may have a top opening at an upper surface of the printedcircuit board and a bottom opening at a lower surface of the printedcircuit board.

In the step illustrated in FIG. 11C, a plurality of interior conductiveleads are placed to a plurality of conductive pads near the cavity andfixed on the upper surface of the printed circuit board by solderingsuch that each of the conductive leads may have a first lead portionsubstantially laterally extending from the conductive pads to an edge ofthe cavity; and a second lead portion bending from the first leadportion and extending substantially longitudinally downward along aninterior sidewall into the cavity. In some embodiments, each of theconductive leads may further have a third lead portion bending from thesecond lead portion and extending substantially laterally towards acentral region of the cavity.

FIG. 12A shows more details of the top view of the printed circuit board50B and FIG. 12B is a cross sectional view taken along the cutting lineA-A′ in the FIG. 12A. The printed circuit board 50B of FIG. 12A and FIG.12B is similar to the printed circuit board 50A of FIG. 9A and FIG. 9Bexcept for that the printed circuit board 50B comprise a cavity 510Bthat has a blind-hole structure. For simplicity, identical elements inFIG. 12A and FIG. 12B and FIG. 9A and FIG. 9B are given the samereference numerals and will not be further described in details.

As shown in FIG. 12A and FIG. 12B, the cavity 510B of the printedcircuit board 700 may have a top opening at an upper surface 501 of theprinted circuit board 50B and a bottom base 512B formed at a substratelayer between the upper and lower surfaces of the printed circuit board.

Referring to FIG. 13A and FIG. 13B, similarly, the cavity 510B may havean interior shape conformal to an exterior shape of a semiconductordevice 30A such that the semiconductor device 30A can be removablyfitted into the cavity 510B.

FIGS. 14A, 14B and 14C depict steps of a method for manufacturing aprinted circuit board according to the embodiment of FIG. 12A and FIG.12B. The method as shown in FIGS. 14A, 14B and 14C is similar to themethod as shown in FIGS. 11A, 11B and 11C, except for that in the stepof FIG. 14B, a blind-hole cavity is formed in the printed circuit boardby machine cutting or laser drilling. That is, the cavity may be a blindhole having a top opening at the upper surface of the printed circuitboard and a bottom base at a substrate layer between the upper and lowersurfaces of the printed circuit board.

The foregoing description of the present invention has been provided forthe purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise forms disclosed.Many modifications and variations will be apparent to the practitionerskilled in the art.

The embodiments were chosen and described in order to best explain theprinciples of the invention and its practical application, therebyenabling others skilled in the art to understand the invention forvarious embodiments and with various modifications that are suited tothe particular use contemplated.

As used herein and not otherwise defined, the terms “substantially,”“substantial,” “approximately” and “about” are used to describe andaccount for small variations. When used in conjunction with an event orcircumstance, the terms can encompass instances in which the event orcircumstance occurs precisely as well as instances in which the event orcircumstance occurs to a close approximation.

As used herein, the singular terms “a,” “an,” and “the” may includeplural referents unless the context clearly dictates otherwise. In thedescription of some embodiments, a component provided “on” or “over”another component can encompass cases where the former component isdirectly on (e.g., in physical contact with) the latter component, aswell as cases where one or more intervening components are locatedbetween the former component and the latter component.

While the present disclosure has been described and illustrated withreference to specific embodiments thereof, these descriptions andillustrations are not limiting. It should be understood by those skilledin the art that various changes may be made and equivalents may besubstituted without departing from the true spirit and scope of thepresent disclosure as defined by the appended claims.

The illustrations may not necessarily be drawn to scale. There may bedistinctions between the artistic renditions in the present disclosureand the actual apparatus due to manufacturing processes and tolerances.Further, it is understood that actual devices and layers may deviatefrom the rectangular layer depictions of the FIGS. and may includeangles surfaces or edges, rounded corners, etc. due to manufacturingprocesses such as conformal deposition, etching, etc. There may be otherembodiments of the present disclosure which are not specificallyillustrated. The specification and the drawings are to be regarded asillustrative rather than restrictive. Modifications may be made to adapta particular situation, material, composition of matter, method, orprocess to the objective, spirit and scope of the present disclosure.All such modifications are intended to be within the scope of the claimsappended hereto.

While the methods disclosed herein have been described with reference toparticular operations performed in a particular order, it will beunderstood that these operations may be combined, sub-divided, orre-ordered to form an equivalent method without departing from theteachings of the present disclosure. Accordingly, unless specificallyindicated herein, the order and grouping of the operations are notlimitations.

1. A printed circuit board suitable for implementation of asemiconductor device, comprising an upper surface; a lower surfaceopposite to the upper surface; one or more substrate layers arrangedbetween the upper surface and the lower surface; a cavity having one ormore interior sidewalls being substantially perpendicular to the upperand lower surfaces; and a plurality of interior conductive leads fixedon and extending from the upper surface of the printed circuit board andbending into the cavity; wherein the cavity of the printed circuit boardhas a shape conformal to a shape of an enclosure of the semiconductordevice such that the semiconductor device can be removably press-fittedinto the cavity of the printed circuit board; and wherein the pluralityof interior conductive leads in the cavity of the printed circuit boardare configured to be resiliently contactable to and electricallycouplable with a plurality of exterior conductive contacts of thesemiconductor device such that the cavity act as an electrical socketcooperating with an electrical plug acted by the semiconductor device.2. The printed circuit board according to claim 1, wherein each of theinterior conductive leads comprises: a first lead portion fixed on aconductive pad on the upper surface and extending from the conductivepad to an edge of the cavity; a second lead portion bending from thefirst lead portion and extending substantially longitudinally downwardalong one of the interior sidewalls into the cavity.
 3. The printedcircuit board according to claim 2, wherein the second lead portion iselastically deformable to have a resilient contact with the exteriorconductive contacts of the semiconductor device when the semiconductordevice is inserted into the cavity.
 4. The printed circuit boardaccording to claim 3, wherein the second lead portion is pushed by thesemiconductor device and having a movable end flushing against theinterior sidewall in the cavity such that the second lead portion isdeformed to have a substantially flat surface coupling with the exteriorconductive contacts of the semiconductor device when the semiconductordevice is inserted into the cavity
 5. The printed circuit boardaccording to claim 1, wherein the cavity has a through-hole structure.6. The printed circuit board according to claim 1, wherein the cavityhas a blind-hole structure.
 7. A semiconductor module, comprising: aprinted circuit board, comprising: an upper surface; a lower surfaceopposite to the upper surface; one or more substrate layers arrangedbetween the upper and lower surfaces; a cavity having one or moreinterior sidewalls being substantially perpendicular to the upper andlower surfaces; a plurality of interior conductive leads fixed on andextending from the upper surface of the printed circuit board andbending into the cavity; a semiconductor device having an enclosure anda plurality of exterior conductive contacts exposed on a plurality ofside surfaces of the enclosure; wherein the cavity of the printedcircuit board and the enclosure of the semiconductor device have shapesconformal to each other such that the semiconductor device can beremovably press-fitted into the cavity of the printed circuit board; andwherein the plurality of exterior conductive contacts of thesemiconductor are configured to be contactable to and electricallycouplable with the plurality of interior conductive leads in the cavityof the printed circuit board such that the semiconductor device act asan electrical plug cooperating with the cavity which act as anelectrical socket.
 8. The semiconductor module according to claim 7,wherein the cavity of the printed circuit board has a through-holestructure.
 9. The semiconductor module according to claim 8, furthercomprising a first heatsink mounted on a top surface of thesemiconductor device and a second heatsink mounted on a bottom surfaceof the semiconductor device.
 10. The semiconductor module according toclaim 7, wherein the cavity of the printed circuit board has ablind-hole structure.
 11. The semiconductor module according to claim10, further comprising a first heatsink mounted on a top surface of thesemiconductor device.
 12. A method for manufacturing a printed circuitboard suitable for implementation of a semiconductor device, comprising:providing a printed circuit board patterned with conductive traces andpads on an upper surface and a bottom surface; forming a cavity in theprinted circuit board; and placing and fixing a plurality of interiorconductive leads respectively to a plurality of conductive pads near thecavity and on the upper surface of the printed circuit board such thateach of the conductive leads has a first lead portion substantiallylaterally extending from the conductive pads to an edge of the cavity;and a second lead portion bending from the first lead portion andextending substantially longitudinally downward along an interiorsidewall into the cavity; wherein the cavity of the printed circuitboard has a shape conformal to a shape of an enclosure of thesemiconductor device such that the semiconductor device can be removablypress-fitted into the cavity of the printed circuit board; and whereinthe plurality of interior conductive leads are configured to beresiliently contactable to and electrically couplable with a pluralityof exterior conductive contacts of the semiconductor device such thatthe cavity act as an electrical socket cooperating with an electricalplug acted by the semiconductor device.